The subject matter of this application relates to a method of operating a router.
Referring to FIG. 1 of the drawings, a television program provider may operate a production facility 6 at which it produces a digital television (DTV) program signal AV having a baseband video component representing a sequence of pictures and a corresponding baseband audio component. We will assume for the purpose of this discussion that the baseband video component is in the high definition serial digital interface (HD-SDI) format specified in SMPTE 292M and that the baseband audio component includes at least one channel of digital audio data that is encoded in accordance with the standard known as AES3 and is embedded in the horizontal ancillary data space of the HD-SDI video signal (defined by SMPTE 292M) in accordance with the mapping defined in SMPTE 299M. It will be understood by those skilled in the art that the HD-SDI video signal is able to accommodate up to 16 audio channels, organized as four groups each containing four audio channels. Typically, a channel of the baseband audio component is derived from an analog audio signal that has been sampled at 48 kHz, and each line of the horizontal ancillary (HANC) data space of the HD-SDI signal carries 0, 1 or 2 audio samples.
In accordance with the AES3 standard, each audio data sample has 20 or 24 bits and is placed in an AES subframe having 32 bits. Four bits of the subframe form a preamble that is used for synchronizing purposes. Two AES subframes form an AES frame. Generally, the two audio data samples that are placed in the two subframes of an AES frame are related, for example as left and right channel stereo components, and the mapping scheme maintains a constant time relationship between the two samples through embedding and subsequent disembedding.
For convenience in set up and use of the illustrated equipment there will generally be a consistent mapping between audio signal sources and the channels that convey the respective audio data streams provided by the audio signal sources. For example, the audio data samples derived from left and right channel stereo components of an audio signal would typically be conveyed in two adjacent channels (e.g. channels 1 and 2 or channels 3 and 4) of the HD-SDI signal.
Audio data may alternatively be encoded using Dolby E packets, which may be conveyed using a data structure similar to AES frames. A single Dolby E packet cannot be accommodated by an AES subframe and therefore the Dolby E packet is split into two subpackets that are placed in the two subframes respectively of the AES frame. Thus, in the event that Dolby E packets are embedded in an HD-SDI signal, the two subpackets of the Dolby E packet are conveyed in two adjacent channels respectively.
Still referring to FIG. 1, the program signal is supplied to a program signal router 8 that receives the program signal at an input and directs the program signal to a selected destination via an output of the program signal router. It will be appreciated that the program signal router would normally have many inputs and many outputs and can be configured to direct the program signal received at any selected input to any exclusive set of one or more destinations.
In practice, it may be desirable to switch the audio component of the program signal separately from the video component. This may be accomplished by disembedding the audio component from the program signal, supplying the program signal and the audio component to a video switch 10 and an audio switch 12 respectively, and re-embedding the audio component in the program signal downstream of the video switch 10. In a practical implementation, the video switch is an X-Y space switch having row and column conductors that can be selectively interconnected by crosspoint switch elements whereas the audio switch is a shared memory time switch.
Operation of a shared memory time switch that can route a signal provided by one of four sources to an exclusive set of at least one of four destinations will be described with reference to FIG. 2. Digital data words from respective sources are supplied to input registers 16, each of which is assigned a position in a sequence that contains all the input registers. Typically, the assigned position of an input register 16 reflects the spatial location of an input terminal, such as a connector, to which the input register is connected. A controller (not shown) read enables the input registers sequentially and accordingly the data words are placed sequentially on a bus 18. The controller controls the read enable command supplied to the input registers and the state of the bus 18 so that the data words are placed on the bus in successive bus operating cycles. Consequently, the position of a data word from a particular input register in the sequence of bus operating cycles depends strictly on the assigned position of the input register. The sequence of data words is written to successive addresses in a memory array 20, and the address to which a data word is written depends strictly on the position of the data word in the sequence of bus operating cycles and hence on the spatial location of the input terminal at which the data word was received.
Data words are read from the memory array 20 and each word is placed on an output bus 22 in at least one of four time slots of the bus operating cycle. The output bus thus conveys up to four interleaved digital signals. The switch also comprises four output registers 24 whose outputs are connected respectively to the four output terminals of the switch. Analogously to the input registers, each output register 24 is assigned a position in a sequence that contains all the output registers and typically the assigned position of an output register reflects the spatial location of the output terminal to which the output register is connected. The controller controls the read enable command supplied to the output registers and the state of the bus 22 so that each output register reads the data words that are in an assigned time slot of the bus operating cycle.
The controller receives an operator command specifying the output(s) to which a given input signal is to be directed, and generates read enable commands that will result in the data words of the input signal being routed to the appropriate outputs. Suppose, for example, that the operator sets the controller to select the signal received at the input terminal connected to the input register 161 for routing to the output terminals connected to the output registers 241 and 243. In this case, the controller controls the read enable commands supplied to the memory array so that the data words that were supplied to the memory array in time slot 1 of the bus operating cycle are placed on the output bus in both time slot 1 and time slot 3 of the bus operating cycle. The output registers 241 and 243 read the signal on the output bus in time slots 1 and 3 respectively of the bus operating cycle. Accordingly, the data words of the signal received at the input terminal connected to the input register 161 are routed both to the output terminal connected to the output register 241 and to the output terminal connected to the output register 243.
Referring again to FIG. 1, the audio switch 12 is designed to receive sample words, each containing one audio sample, from the disembedder 26 at a uniform rate of 48 ks/s and supply sample words to the embedder 28 at a uniform rate of 48 ks/s. Because the number of audio samples per line of the video signal varies between 0 and 2, a FIFO register 30 at the input of the audio switch 12 is used to match the rate at which the disembedder outputs sample words to the rate at which the switch 12 receives sample words, and similarly a FIFO register 32 at the output of the audio switch is used to match the rate at which the switch 12 supplies sample words to the rate at which the embedder 28 receives sample words. In order to ensure that a sample word is always available to read from the input FIFO 30 when required by the audio switch, the input FIFO must be able to contain up to 64 sample words and, on average, it contains 32 sample words. Similarly, in order to meet the demands of circuitry that specifies the number of samples that the embedder must insert on each line of the video signal, the output FIFO 32 must be able to contain up to 64 sample words and its average content is 32 sample words. Consequently, the average delay suffered by an audio sample in passing through the FIFOs and the audio switch is 64 sample times plus the delay through the audio switch (between 3 and 5 sample times), or about 1.43 ms. In comparison, the delay suffered by the video component of the HD-SDI program signal in passing through the video switch is negligible. This difference in delay between the video component and the audio component may cause objectionable lip sync error.